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Design and analysis of novel organic thin film multiplexer |
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| รหัสดีโอไอ | |
| Creator | Pawan K. Mishra |
| Title | Design and analysis of novel organic thin film multiplexer |
| Contributor | Arun Pratap S. Rathod |
| Publisher | Khon Kaen University, Thailand |
| Publication Year | 2568 |
| Journal Title | Asia-Pacific Journal of Science and Technology |
| Journal Vol. | 30 |
| Journal No. | 6 |
| Page no. | 5 (12 pages) |
| Keyword | Multiplexer, OTFT, Organic electronics, Thin films, CMOS, OTFM |
| URL Website | https://apst.kku.ac.th/ |
| Website title | https://apst.kku.ac.th/design-and-analysis-of-novel-organic-thin-film-multiplexer/ |
| ISSN | 2539-6293 |
| Abstract | In recent years a transition from conventional electronic devices based on silicon to organic material based electronic devices has been observed. As the market for flexible and wearable devices has presented greater opportunities and sharp growth, the demand for organic thin film transistor (OTFT) based combinational circuits has increased exponentially. Traditionally such circuits were fabricated through complementary metal oxide semiconductor (CMOS) logic architecture, but due to large number of nodes OTFTs employed in circuit implementation, the overall power consumption, interconnect delay and the chip area of the circuit increases significantly. Organic thin film multiplexer (OTFM) is a novel attempt to redesign an existing multi-transistor combinational logic device like 2:1 Multiplexer in the form of a single multi-layered logical device, while maintaining the dimensions, material composition and fabrication method equivalent to single OTFT (bottom gate bottom contact OTFT). The design and development of the OTFM has been achieved through Silvaco a large ion collider experiment (ATLAS) technology computer-aided design (TCAD) tool while the examination of power and area consumption of the OTFM and equivalent CMOS circuit was accomplished through post layout (physical design) analysis using Cadence Virtuoso exploratory data analysis (EDA) tool. It has been found in this research that the power and chip area consumption of proposed OTFM is lower than that of CMOS logic based 2:1 Multiplexer by 90% and 95% (approx.) respectively, while operating under same voltage regime for implementing identical logical functions. |
